Can this be thru ? - GSM-Forum

Gsmhq · 10-24-2003, 14:37

if you got special phoenix version, which work with special PKD-1, then you can have "RD" ( like PC-local) in phoenix ,, and READ/WRITE UPP, UEM, AEM , DSP, MCU, PPM, any address

Gsmhq · 10-24-2003, 15:05

here is some other information to..

Flash programming:
The actual programming is indicated to the UPP by using the MBUS_RX signal between the UPP and the UEM. The MBUS signal from the UEM to the flash prommer (FPS8 box) is used as clock for the synchronous communication. The flash prommer keeps the MBUS line low during UPP boot, to indicate that the flash prommer is connected. If the UPP MBUS_RX signal is low on UPP, the MCU enters flash programming mode. If the signal is high, the MCU starts loading software from the flash.
In order to avoid accidental entry to the "flash programming mode" the MCU only waits for a specified time, to get input data from the flash prommer. If the timer expires without any data being received, the MCU will continue the boot sequence. The MBUS signal from UEM to the external connection is used as clock during flash programming. This means that flash programming clock is supplied to the UPP on the MBUS_RX signal. The flash prommer indicates to the UEM that flash programming/reprogramming by writing an 8 bit password to the UEM. The data is transmitted on the FBUS_RX line and the UEM
clocks the data on the FBUS_RX line into a shift register. When the 8-bits have been shifted in the register, the FPS8-box generates a falling-edge on the BSI line. This loads the shift register content in the UEM into a compare register. These 8-bits will be compared in a register to see if they match the "secret" default value inside the UEM. At this point the flash prommer must pull the MBUS signal to UEM low, in order to indicate to the MCU that the flash prommer is connected. The UEM reset-state machine performs a reset to the system (PURX low for 10–100 ms). The UEM "flash programming mode" is valid until MCU sets a bit in the UEM register, which indicates the "end of flash programming". Setting this bit also clears the compare register in the UEM previously loaded, at the falling edge of the BSI signal. During the "flash programming mode" the UEM watc-dog is disabled. When the bit is set it indicates "end of flash programming" and it resets the UEM watchdog timer to it’s default value. Clearing the flash programming bit also causes the UEM to generate a reset to the UPP. The BSI signal is used to load the value into the compare register. In order to avoid spurious loading of the register, the BSI sig-nal will be gated during UEM "master-reset", and during "power-on" when PURX is active. The BSI signal should not change state during normal operation unless the battery is extracted, in this case the BSI signal will be pulled high, note a falling edge is required to load the compare register.

10-24-2003, 14:37	#1 (permalink)
Gsmhq No Life Poster Join Date: Dec 1999 Location: Sweden Age: 35 Posts: 783 Member: 739 Status: Offline Thanks: 0 Thanked 0 Times in 0 Posts	Can this be thru ? if you got special phoenix version, which work with special PKD-1, then you can have "RD" ( like PC-local) in phoenix ,, and READ/WRITE UPP, UEM, AEM , DSP, MCU, PPM, any address

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10-24-2003, 15:05	#2 (permalink)
Gsmhq No Life Poster Join Date: Dec 1999 Location: Sweden Age: 35 Posts: 783 Member: 739 Status: Offline Thanks: 0 Thanked 0 Times in 0 Posts	here is some other information to.. Flash programming: The actual programming is indicated to the UPP by using the MBUS_RX signal between the UPP and the UEM. The MBUS signal from the UEM to the flash prommer (FPS8 box) is used as clock for the synchronous communication. The flash prommer keeps the MBUS line low during UPP boot, to indicate that the flash prommer is connected. If the UPP MBUS_RX signal is low on UPP, the MCU enters flash programming mode. If the signal is high, the MCU starts loading software from the flash. In order to avoid accidental entry to the "flash programming mode" the MCU only waits for a specified time, to get input data from the flash prommer. If the timer expires without any data being received, the MCU will continue the boot sequence. The MBUS signal from UEM to the external connection is used as clock during flash programming. This means that flash programming clock is supplied to the UPP on the MBUS_RX signal. The flash prommer indicates to the UEM that flash programming/reprogramming by writing an 8 bit password to the UEM. The data is transmitted on the FBUS_RX line and the UEM clocks the data on the FBUS_RX line into a shift register. When the 8-bits have been shifted in the register, the FPS8-box generates a falling-edge on the BSI line. This loads the shift register content in the UEM into a compare register. These 8-bits will be compared in a register to see if they match the "secret" default value inside the UEM. At this point the flash prommer must pull the MBUS signal to UEM low, in order to indicate to the MCU that the flash prommer is connected. The UEM reset-state machine performs a reset to the system (PURX low for 10–100 ms). The UEM "flash programming mode" is valid until MCU sets a bit in the UEM register, which indicates the "end of flash programming". Setting this bit also clears the compare register in the UEM previously loaded, at the falling edge of the BSI signal. During the "flash programming mode" the UEM watc-dog is disabled. When the bit is set it indicates "end of flash programming" and it resets the UEM watchdog timer to it’s default value. Clearing the flash programming bit also causes the UEM to generate a reset to the UPP. The BSI signal is used to load the value into the compare register. In order to avoid spurious loading of the register, the BSI sig-nal will be gated during UEM "master-reset", and during "power-on" when PURX is active. The BSI signal should not change state during normal operation unless the battery is extracted, in this case the BSI signal will be pulled high, note a falling edge is required to load the compare register.