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Go Back   GSM-Forum > GSM & CDMA Phones / Tablets Software & Hardware Area > Nokia > Nokia Base Band 5 ( BB-5 )

Nokia Base Band 5 ( BB-5 ) Baseband-5 Phones: 2700 Classic , 2730 Classic , 3109c , 3110c , 3120c , 3250 , 3500c , 3600s , 3610 Fold , 3710 Fold , 3720 Classic , 5130 XpressM , 5200 / 5200b , 5220 XpressM , 5230 XpressM , 5300 / 5300b , 5310 / 5310b , 5320 , 5500 , 5530 XpressM , 5610 , 5630 XpressM , 5700 , 5730 XpressM , 5800 , 6085 / 6086 , 6110n , 6120c , 6121c , 6124c , 6125 , 6126 / 6133b , 6131 / 6133 , 6131 (NFC) , 6136 , 6151 , 6208 Classic , 6210n , 6212c , 6220c , 6233 , 6234 , 6260 Slide , 6263 , 6267 , 6270 , 6280 / 6288 , 6282 , 6290 , 6300 , 6300i , 6301 , 6303 Classic , 6500 Classic , 6500 Slide , 6555 , 6600 Fold , 6600 Slide , 6630 , 6650 Fold , 6680 , 6681 , 6682 , 6700 Classic , 6710 Navigator , 6720 Classic , 6730 Classic , 6760 Slide , 6790 Surge , 7210c , 7310c , 7370 , 7373 , 7390 , 7500 , 7510c , 7610c , 7900 , 8600 , 8800 arte , E50 , E51 , E52 , E55 , E60 , E61 , E61i , E62 , E63 , E65 , E66 , E70 , E71 , E72 , E75 , E90 , N70 , N71 , N72 , N73 , N75 , N76 , N77 , N78 , N79 , N80 , N81 , N82 , N85 , N86 , N90 , N91 , N92 , N93 , N93i , N95 , N95 8GB , N96 , N97 , N97 Mini , X3 , X6

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Old 11-11-2006, 23:33   #1 (permalink)
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bb5 unlock manual

the block resides in this chip:
manually the block can be removed, with proper equipments and interface the PBA with a special hardware

K8S5615ETA
256M Bit (16M x16) Muxed Burst , Multi Bank NOR Flash Memory



General Description Features Package & Packing

Production & Availability Specification Data Material Data Declaration Sheet

Declaration Letter




General Description

The K8S5615E featuring single 1.8V power supply is a 256Mbit Muxed Burst Multi Bank Flash Memory organized as 16Mx16. The memory architecture of the device is designed to divide its memory arrays into 519 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capability. The K8S5615E NOR Flash consists of six**** banks. This device is capable of reading data from one bank while programming or erasing in the other bank.
Regarding read access time, the K8S5615E provides an 14.5ns burst access time and an 88.5ns initial access time at 54MHz. At 66MHz, the K8S5615E provides an 11ns burst access time and 70ns initial access time. The device performs a program operation in units of Single 16 bits (word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/erase current in the extended temperature ranges.
The K8S5615E NOR Flash Memory is created by using Samsung's advanced CMOS process technology. This device is available in 44 ball FBGA package.


Features

Single Voltage, 1.7V to 1.95V for Read and Write operations
Organization
- 16,777,216 x 16 bit ( Word Mode Only)
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
Read While Program/Erase Operation
Multiple Bank Architecture
- 16 Banks (16Mb Partition)
OTP Block : Extra 256Byte block
Read Access Time (@ CL=30pF)
- Asynchronous Random Access Time : 90ns (54MHz) / 80ns (66MHz)
- Synchronous Random Access Time : 88.5ns (54MHz) / 70ns (66MHz)
- Burst Access Time : 14.5ns (54MHz) / 11ns (66MHz)
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
Block Architecture
- Eight 4Kword blocks and five hundreds eleven 32Kword blocks
- Bank 0 contains eight 4 Kword blocks and thirty-one 32Kword blocks
- Bank 1 ~ Bank 15 contain four hundred eighty 32Kword blocks
Reduce program time using the VPP
Support Single & Quad word accelerate program
Power Consumption (Typical value, CL=30pF)
- Burst Access Current : 30mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 25uA
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=VIL
- All blocks are protected by VPP=VIL
Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
Erase Suspend/Resume
Program Suspend/Resume
Unlock Bypass Program/Erase
Hardware Reset (RESET)
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program or erase completion
Endurance
100K Program/Erase Cycles Minimum
Data Retention : 10 years
Extended Temperature : -25C ~ 85C
Support Common Flash Memory Interface
Low Vcc Write Inhibit
Package : 44 - ball FBGA Type, 8x11mm, 0.5 mm ball pitch, 1.0mm (Max.) Thickness
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