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09-18-2012, 05:23 | #21 (permalink) |
Freak Poster Join Date: May 2007
Posts: 498
Member: 515830 Status: Offline Thanks Meter: 80 | nice to see big boys making toys and thanks for let us read the research y development backstage my 3 whishes for the genie: 1-standalone 2-ultra hard hard test point. 3-$$$$$$$$$ |
09-18-2012, 08:10 | #22 (permalink) |
No Life Poster Join Date: Feb 2000 Location: UK
Posts: 3,186
Member: 1024 Status: Offline Thanks Meter: 5,510 | Good morning, Just recall some design problems with the old Dejan's TP unlock. It had similar problem with two masters on the same bus(back then was CFI flash and box). So here the problem with enforcing logic high is resolved with a bit higher level on the bus. The more difficult problem is enforcing low on the bus. The internal transistor on the GPIO pin on a typical microcontroller can not do that as the output impedance is quite high in open state. ATF box has the advantage of configurable FPGA that allows bridging few high drive gates in parallel to an output pin and create low impedance load. It is possible this way to assert low, when say the Qcom cpu tries to force the bus to high. So it might be not possible to implement this on standard microcontroller at all. BR |
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09-18-2012, 11:33 | #23 (permalink) | |
No Life Poster Join Date: Feb 2005 Location: Poland Age: 34
Posts: 4,943
Member: 117496 Status: Offline Sonork: 100.83919 Thanks Meter: 22,689 | Quote:
But not a problem to solder another testpoint (eMMC VCC, R1519 resistor @ NK 800) and DON'T POWER TARGET BOARD (CPU+PM8058+...), just power eMMC via box... then "two masters" problem disappears and eMMC can be read/written easily, as MCU becomes only one master on SPI bus. | |
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09-18-2012, 11:50 | #24 (permalink) |
No Life Poster Join Date: Feb 2005 Location: Poland Age: 34
Posts: 4,943
Member: 117496 Status: Offline Sonork: 100.83919 Thanks Meter: 22,689 | About dejan hack: It was bit diffrent. FPGA was attached as a slave (it didn't generated own clock - only captured data at AD0,AD1,ADx, on rising/falling flash clock edges generated by CPU) and when pattern was matched, put ADx high/low. So x ns job. Here need to FULL capture 2 lines for SO long time. And remember: in dejan hack target CPU needs to be WORKING (because it patched return jump from PA call on-the-fly), so it needed to execute rest part of code (re-create pm-308,etc..).. Here we don't need have system running - that's why we can deal with eMMC directly. |
09-18-2012, 13:48 | #25 (permalink) |
No Life Poster Join Date: Feb 2000 Location: UK
Posts: 3,186
Member: 1024 Status: Offline Thanks Meter: 5,510 | Hi, Yes all true, but still was the same challenge on phones that needed bit cleared in the jump instruction. Phones with bit set, could have been done easy with MCU GPIO - np. BR |
09-18-2012, 15:51 | #26 (permalink) |
Freak Poster Join Date: Sep 2005 Location: at virgin galatic
Posts: 293
Member: 184884 Status: Offline Thanks Meter: 564 | some birds in nokia told me : can be reset all the "data " for emmc specially "dead" emmc after reset by third party software with special" trick " hope can be done too from all programer in here |
09-20-2012, 00:41 | #28 (permalink) | |
No Life Poster Join Date: Feb 2005 Location: Poland Age: 34
Posts: 4,943
Member: 117496 Status: Offline Sonork: 100.83919 Thanks Meter: 22,689 | Quote:
Full backward compatibility with legacy Multi Media Card system. Ą¤ Data bus width: 1bit /4bit /8bit What is 1bit "legacy" MMC data bus compatiblity? Isn't SPI native 1 bit bus Source: Hynix Newsletter | |
09-20-2012, 08:03 | #29 (permalink) | |
Freak Poster Join Date: Mar 2004 Location: Romania Age: 48
Posts: 408
Member: 59869 Status: Offline Thanks Meter: 132 | Quote:
A lot of phones are using I²C protocol (SCL&SDA).As I see in the schematics, Lumia is using 8bit data bus width between eMMC and MSM8255. But enough with my off-topic. | |
09-20-2012, 15:18 | #30 (permalink) | |
No Life Poster Join Date: Feb 2005 Location: Poland Age: 34
Posts: 4,943
Member: 117496 Status: Offline Sonork: 100.83919 Thanks Meter: 22,689 | Quote:
You are right, wikipedia say SPI uses 4 wires. THIS is true, because basic spi uses 4 wires: Clock - generated by master device Mosi - can say is "TX" from master side Miso - can say is "RX" from master side CS - chip select How do you think, how many bits is send during one clock cycle? ( i skip DDR situation, when data are captured on both falling and rising edges of clock ). I tell you: SPI transmission is pure full duplex. So, during one clock cycle, a 1 bit of data will be exchanged between master and slave - and vice versa. That's why this bus is called "1 bit" bus. CS is not data signal, is only asserted on multi-slave SPI configurations, so Slave device know data is addressed to it's device. So, basic SPI version is 1-bit only. Also read MMC specs. MMC controller might be initialized to use 1-bit SPI mode, but you may also use it in 4-bit or 8-bit mode... all just for compatibility. That's why during normal phone operation, eMMC is clocked 50MHz, and during one clock cycle all 8 bit are used. BUT you can always re-INIT eMMC and force it to use 1 bit mode... as its 100% conforms MMC standard I don't see any problem. Last edited by karwos; 09-20-2012 at 15:26. | |
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